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There are 4 questions in total, please answer all of them.And the answer should be typed, for some problem need to draw the graph, you can draw it by hand, other questions should be typed.CSE140 Winter 2021 Homework 3
Due Feb. 4 11:59PM PST – Gradescope submission
(Grade out of 100; each problem is worth 50pts, we grade 2)
Q1: ​Fill in the following table with the corresponding operations computed (G in the diagram) in
terms of multi-bit inputs A and B given the control signals F 0 , F 1 , F 2 , F 3 . Note that the shifters
are only shifting one place.
F3
F2
F1
F0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Operation
Q2: ​Design a circuit that takes a 4-bit input A = A​3​A​2​A​1​A​0​ and generates an output Z = Z​3​Z​2​Z​1​Z​0
based on a 2-bit select signal S = S​1​S​0​.
Implement the above functionality using 1-bit full adders, 2:1 multiplexers, and NOT gates. The
select signal should support the following scenarios.
● If S = 00, Z is generated by adding 1 to the input (increment by 1)
● If S = 01, Z is generated by subtracting 1 from the input (decrement by 1)
● If S = 10, Z is just A
● If S = 11, Z is two’s complement of A
You can assume that constant signals (1/0) are available as inputs.
Q3: ​For the latch shown below, fill out the truth table and show the characteristic equation of the
circuit.
X
Y
Q(t)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Q(t+ Δ )
Q’(t+ Δ )
Q4.
We want to design a basic decimal calculator, which can be used to add or subtract 2-digit (from
-99 to +99) decimal numbers. We will attempt to design a logic circuit that accepts two signed
integers A and B, and a control signal Z, which is set to 0 for addition and 1 for subtraction, and
outputs the result as an 8-bit binary number in its 2’s complement representation.
The input BCD numbers A and B will be represented as:
Asign = 0 f or A ≥ 0 , and Asign = 1 f or A < 0 . Further, we use 8 bits to represent the 2 digits of A as follows: If A = (+ 93)10 , then Asign = 0 and A7 A6 A5 A4 represent the binary form for the tens digit of A (9)10 = 1001 and A3 A2 A1 A0 := 0011 = 3 represent the unit's place for A. (+ 93)10 = 0 1001 0011 If A = (− 47)10 , we just change the sign bit: (− 47)10 = 1 0100 0111 The MSB is the sign bit. a) The first part of the design involves converting the BCD into its equivalent binary magnitude (Eg: -34 and 34 in BCD are both converted to 00100010 in binary magnitude). In this design, you can use ​n-b ​ it adders and multipliers with 2 4-bit inputs and one 8-bit output. b) Now, we will convert the binary representation of A and B, into their equivalent 2’s complement notation. At this step, we will take into account whether we are adding or subtracting A and B, using gate MG. What is the truth table for MG? c) We wish to create an overflow detector, which can detect the nature of the overflow. The output O from the adder is set to 1 if an overflow is detected. If there is no overflow, we set E​1 =0 and E​2 =0. If an overflow is detected, and the final sum 127, then we set E​1 =1 and E​2 =1, . Identify the truth table for E​1 and E​2 in terms of A​sign​, B​sign and O, and implement it using only NAND and NOT gates. Purchase answer to see full attachment

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